Documentation of hi-speed devices

[Black Phoenix]

Okay, this reference is targeted at those who want to effectively use advanced things like console screen with CPU.

Intro:
What are hi-speed links? Well, in few words, they allow you to directly access variables/memory of another device, bypassing the regular wire interface. For example, we have the RAM, and we want to write 100 values in it, via CPU. We could connect clock, data, and writeaddress to ports, and write single value. Lets see, it takes at least 2 operations for setting current value, plus the loop, plus the speed of wire system (which limits us). That can be something like 10 seconds. Not much?
Now, we have the hi-speed link. We can access the RAM via the CPU memory. If you connected RAM directly to CPU, then RAM will "live" on top of CPU internal RAM, i.e. starting from address 65536 and further.
Okay, we just write values from 65536 to 65635 (100 values). One instruction per value, and same speed as CPU. You see, copying 100 values here would be 100% equal to copying them into internal CPU RAM.
100 values will be copied instantly (at speed of 5khz for example).
Or you know, you can copy them via the MCOPY opcode, and that will be even faster...

To sum up, hi-speed allows us to gain access to some device just as we were accessing CPU RAM, starting from address 65536.

To use Hi-Speed link system you have to make an i/o link between a device (CPU for example) and another device, just like the regular devices.
For example to connect Console Screen to CPU you will have to connect CPU memory input to console screen memory output with your Wire tool. If destination device has more than one output, its okay to connect to any output. Note that these outputs may act as regular value output too.

We will call the memory of device "device address space"

Lets begin now.

Zyelios CPU
Hi-Speed inputs: MemBus, IOBus
Hi-Speed outputs: Error/Memory

CPU has 2 address spaces: the memory address space and the i/o address space. The only difference between them is that you access the memory space using memory pointers, and i/o space using ports (port0,port234,etc.).
Also, number of ports is limited to 1024, while you can have as much memory as you want.

CPU Memory Space addresses 0..65535 are occupied by internal CPU RAM, the one where program is stored, along with various variables.
By connecting hi-speed device to MemBus input, we link it to addresses 65536, and further. Lets see the example:
We have some device X linked to MemBus input. Lets say device X will print what address it recieves, and what value it recieves when we write to it.
For CPU the memory of our device is situated on addresses starting from 65536.
Lets write to it. Writing 65537 and value 123 will make our device to display "1 - 123". But why?
We wanted address 65537. Device starts from 65536. So that means that we access address 65537-65536 = 1 (remember that addresses start from 0) which is second value.

If you exceed the device address range you will recieve CPU error (memory fault)

IOBus is pretty same, if you would connect the same device X to IOBus input, and output 123 to port4 you will see "4 - 123" (port4 means address 4, again starting from 0)

The only CPU output is hi-speed link to the CPU memory (also thats error value). You can use it as RAM.

RAM
Hi-Speed outputs: Memory/Data

Nothing to add here, it acts like RAM should. You can write/read values from it (notice that toggle/sr latches/etc have only 1 value). Exceeding the limits will result in CPU error.

Address bus
Hi-Speed inputs: Memory1..Memory4
Hi-Speed outputs: Memory

This device is very handy - it can "connect" few address spaces/devices together. What that means? For example we can have device A having memory addresses 0..128, second device will be 256..1023, etc.

You set up offset and size of "block" for each device. If block size wont match to the device address space size, then:
A ) If you read beyond device limits, you will get 0 value (not error)
B ) If device address space is bigger then the size you specified, then the rest after final address will be "cut", and not accessible.

Address spaces can overlap, and in case they do:
A ) When you read, the value will be read from address space with lower number
B ) When you write, the value will be written to all address spaces

Data port
Hi-Speed outputs: Memory (all ports)

This device acts like the ports acted in previous versions of CPU. It has 8 inputs and 8 outputs.
When you write to some address (in range of 0..7) it outputs this value on the related output.
When you read from some address, it returns value of related input.

You can use this to "communicate" with devices which have no hi-speed interface.

Console screen
Hi-Speed outputs: Memory

Console screen has 2 memory areas:
0..1080 - The video memory (what is displayed on screen)
1081..2048 - Internal registers & reserved area.

Format of video memory:

Content: Character | Parameter | Character | Parameter | ...
Address:     0           1           2           3

Character holds the ASCII code of displayed character.
Parameter holds the parameters of previous character.
Low 3 digits of parameter hold foreground color, encoded in 3-digit RGB (each digit shows shade of red,green,blue respectively)
High 3 digits hold background color. If 7th digit is equal to 1 then this character will flash (background and foreground changing places).

Address | Meaning
----------------------------------------------
2031    | Low shift column
2032    | High shift column
2033    | Low shift row
2034    | High shift row
2035    | Charset, always 0
2036    | Brightness (-127..127)
2037    | Shift cells * Obsolete *
2038    | Shift rows (number of rows, >0 shift down, <0 shift up)*****
2039    | Clear Row (Written value specifies the row)
2040    | Clear Column (Written value specifies the column)
2041    | Clear Screen
2042    | Background Color*
2043    | Cursor Blink Rate, in seconds
2044    | Cursor Size, in percent**
2045    | Cursor Address
2046    | Cursor Enabled
2047    | Clk****

* - When BG color is 000, it will be replaced with this color.
** - For example 0.25 will mean 1/4 of character height
*** - "Freezes" the image when set to 0
**** - Same as "clk" input
***** - Use this to move portion of image up/down/left/right without speed loss (no need to copy data!)

Digital screen
Hi-Speed outputs: Memory

Pretty much same as console screen, except here each byte is a dual-pixel.
Format of a pixel:

RGBGGG

GGG - Value of gray, 0..255
RGB - Color encoded in 3-digit RGB (each digit shows shade of red,green,blue respectively).

Address | Meaning
----------------------------------------------
2039    | Clear Row (Written value specifies the row)
2040    | Clear Column (Written value specifies the column)
2041    | Clear Screen
2047    | Clk

Keyboard
Hi-Speed outputs: Memory/Key

Keyboard! You push keys, and it reacts! By default it outputs last pressed key to its only output, BUT the only output also serves as hi-speed link..!
Virtual memory area thing of wired keyboard is divided into 2 areas: 1 is the key buffer, and other one is array of pressed keys.

Key buffer is situated at first 32 bytes of keyboard, and it has following structure:
Zeroth byte shows how much keys there are in the buffer. New keys are appended on start.
Writing value to ANY of these 32 bytes except first will clear value you wrote from key buffer. I.e. if our buffer looks like:
4,2,3,4,5
it means that there are 4 variables. If we write "3" to it, it will become:
3,2,4,5
Writing removes most recent entry of key.
Ideally you'd read a key, trigger your event, and write back this code to same position you read it from.

Writing value to first value clears ENTIRE buffer.

There is also other area, which is situated from 32 bytes and up. It is ASCII-mapped array, where for each byte it's value shows if key is pressed or no.
I.e. if we wanna know if key #48 is pressed (thats "0") we look what is at address 32+48. If theres 1, we're off! Else meh, bad luck, key isn't pressed yet.

[Qjet]

could you clarify the connection of ports to the CPU? You say we can have 1024 ports, yet you can only connect one port to the IO output of the chip

and its like there is an input and output for IO and memory. In addition it seems all i can do is connect ports to the IO output (or input) by using one of the ports them selfs, theirs no output and input built into the ports for this connection. It's so strange and VERY vague.

edit: lets say you connect port0 out of a port chip to the IO of a CPU. what happens when you set the out ports value? then again, can you even set the out ports value since the port chip itself is plugged into the cpus IN IO. Does this mean you can only have 8 outgoing ports but as many ingoing ports as you want??

cause in this state of affairs CPU is almost unusable, its sort of gotten strange

another question: Why is it i have to use the gate chip model? I mean that thing has a large polygon count, and i like mini chips, and is it inconceivable that someone would use nanochips along with a circuit board?

[Black Phoenix]

I think answer to you is this:
1) It does not matter what value you output to the IOBus or MemBus input. CPU ignores them. Its the link which is important, so if you have CPU linked to port0, feel free to use port0 for anything else.
2) About 1024 ports: You can use address bus to connect few data port entities together in one address space. Then you just link it to IOBus.
3) I will change models when I get suitable ones

To easily work with CPU as it was before just connect IOBus to any, any output of ports. Then use the ports entity as if you were using old CPU, do not worry about the link. You can forget about it.

[Neotracer]

if i get it right i can conect eg. 4 data ports to on adressbus with setings

Addr. Space 1 Off: 0 - Size: 8
Addr. Space 2 Off: 8 - Size: 8
Addr. Space 3 Off: 16 - Size: 8
Addr. Space 4 Off: 24 - Size: 8

and the data port conectet to mem 1 will rout the port 0-8 output of cpu to port 0-8 of this data port.
and the data port conectet to mem 3 will rout the port 16-23 output of cpu to port 0-8 of this data port ....aso.
for eg in cpu mov port24,1 will output a 1 on the port0 of the data port conectet to mem 4.

is this corect?

[Black Phoenix]

Yeah you are right, if you connect address bus to IOBus input

[Neotracer]

Yeah you are right, if you connect address bus to IOBus input[/b]

jeah now i understand the new system, but what about conecting more?
cann i conect 4 adressbus to one adressbus to split? ( or even 4 adress buses to each of thes 4 )
(alredy think the answer is yes)

[Black Phoenix]

Yeah

[Qjet]

Well now i have to ask why we can set the first addresses offset

i mean shouldn't that always be at 0? What if we did set it and left everything else. wouldn't that mean their would be some sort of gap in memory?

65535
lets say we set the first address to start at 100

does that mean we have to go to memory location 65635 and forward to access the memory of the component linked to the CPU?

lets say we have an address bus connected to an address bus
the first address bus has an offset of 0 and a size of 100
the second has an offset of 0 and a size of 110
the second is connected to the first, and the first is connected to the CPU

can we access the last 10 values? Would that throw an error? Would the CPU throw an error immediately?

[Black Phoenix]

First question: it will throw error when trying to access values which are not in any range.

Second question: it will read values only from first address space (of overlapping), but write to all of them.

Second will not cause errors on last 10 addresses, it will work fine.

[Qjet]

first question clarification: so that means that you have to access 65635 right? I mean because that and 100 memory values after it would be in range, but nothing below it before 65535 because the address bus skipped them.

second question clarification: Their are two address buses, separate entities connected together, not spaces

so no theirs no overlapping, the second address bus is larger then the space allocated for it for the first address bus, so what happens can you not access the last 10 values in the second address bus?