ASSEMBLY TUTORIAL & MORE SYNTAX REFERENCE
ZyeliosCPU documentation
Basic CPU description:
- Name: Zyelios CPU rev. 688 (last documentation update)
- 126 opcodes
- Several precision modes (for registers)
- Default: 64-bit floating point
- Available: 32-bit floating point, 8-bit, 16-bit, 24-bit, 32-bit, 48-bit
- 64KB on board RAM + 64KB on board ROM (optional)
- Two address busses: IOBus, MemBus
- 64 terabytes of address space on each of address busses
- Clock input, reset input
- Frequency input (not real CPU frequency, but operations/second)
- Extended mode
- Interrupts and non-masked hardware interrupts
- Page-based protection
- Hi-speed link support
Chapter 1: Basic execution environment
Main registers
EAX,EBX,ECX,EDX - General purpose registers
ESI,EDI,EBP - Memory pointers/general purpose
ESP - Stack pointer
Segment registers
CS - Code segment
SS - Stack segment*
DS - Data segment
ES,FS,GS,KS,LS - Extra segments
SS register is used in pair with ESP to define stack.
Full register table. CPUSET/CPUGET opcode
Besides main and segment registers there are special internal registers, which are modified by certain CPU instructions, OR you can use CPUSET/CPUGET opcode to read/write them.
Code:
REGISTER | NUMBER | DESCRIPTION
---------|--------|------------------------------------------------------------
IP | 0 | Instruction pointer. CPUSET 0,X is equal to JMP X
---------|--------|------------------------------------------------------------
EAX | 1 | Accumulator register
EBX | 2 |
ECX | 3 | Counter register
EDX | 4 | Data register
ESI | 5 | Source index (pointer)
EDI | 6 | Destanation index (pointer)
ESP | 7 | Stack pointer
EBP | 8 |
---------|--------|------------------------------------------------------------
ESZ | 9 | Stack size (for stack underflow check). DEFAULTS TO 65536!
---------|--------|------------------------------------------------------------
CS | 16 | Code segment (WARNING: not read only!)
SS | 17 | Stack segment
DS | 18 | Data segment
ES | 19 | Extra segment
GS | 20 |
FS | 21 | F**ing segment
KS | 22 | Key segment
LS | 23 | Library segment
---------|--------|------------------------------------------------------------
IDTR | 24 | Interrupt description table pointer (CPUSET 24,X = LIDTR X)
CMPR | 25 | Comparsion register (CMP A,B = MOV CMPR,A; SUB CMPR,B)
XEIP | 26 | Current instruction instruction pointer [READ ONLY]
LADD | 27 | Last decoded address, ALSO interrupt parameter register
LINT | 28 | Last called interrupt number
TMR | 29 | Internal clock timer
TIMER | 30 | Internal timer. (CPUGET X,30 = TIMER X)
CPAGE | 31 | Current executed page number [READ ONLY]
---------|--------|------------------------------------------------------------
IF | 32 | Interrupt flag (STI,CLI)
PF | 33 | Compatibility interrupt mode flag (STP,CLP)
EF | 34 | Extended mode flag (STE,CLE)
---------|--------|------------------------------------------------------------
BusLock | 45 | Bus lock flag (CPUSET 45,1 puts CPU into hw halt mode)
Idle | 46 | Idle flag (CPUSET 46,1 = IDLE)
INTR | 47 | Internal interrupt flag (always sets to 0)
---------|--------|------------------------------------------------------------
SERIAL | 48 | CPU SERIAL NUMBER (unique to each single CPU) [READ ONLY]
CODEBYTES| 49 | Size of executed code in bytes [READ ONLY]
BPREC | 50 | Binary precision (default: 48 bits)
IPREC | 51 | Processor precision (default: 0, aka 64 bits floating point)
NIDT | 52 | Forced interrupt table size (interrupts outside the table
| | will be treatened as interrupts with flag set to "0")
Internal CPU memory
ROM is copied into RAM on startup or reset. ROM can be modified using special opcodes.
Access to some memory regions can be denied with paging mechanism (read, write, or execute).
CPU without internal ROM/RAM will start executing from offset 0 of MemBus (memory bus)
Hi-speed links and external memory
You can connect devices to CPU via hi-speed links. Hi-speed links allow you to transfer data much faster than using regular ports (up to 32000 fbytes/second versus only 40 fbytes/second).
When CPU has internal RAM, external memory starts after offset 65536.
So if for example you had device which has range of bytes from 0 to 255 then its new range will be from 65536 to 65536+255.
Same goes for IOBus, but now instead of connecting to memory space we connect to port space. I.e. now we will read values by accessing ports.
For our device these will be ports #0..#255.
Accessing values out of memory range will result in error.
You can connect address spaces using Address Bus.
On processor level IOBus and MemBus are equal, and only sign bit in request address selects IOBus or MemBus (positive addresses are MemBus/CPUROM, negative are IOBus).
Segmentation
Actual address of a byte (called effective address) would be sum of segment register and requested address, which correspond to operation.
Default data register is DS, unless specified otherwise. CS register can be modified only by CALLF or JMPF opcodes.
Code:
EffectiveAdress = Segment + Offset(from instruction)
Stack
Stack is pointed by ESP and SS registers. By default they are set so stack starts from top of CPU ram, and grows down.
ESP register points to next free space on stack, unlike x86.
ESZ register shows stack size which is used for stack underflow checks. It defaults to 65536, and can be modified by CPUSET/CPUGET.
Paging
Entire memory is divided into 128-byte pages. Each page has following parameters:
READ - is reading from here allowed?
WRITE - is writing here allowed?
EXECUTE - is executing this as code allowed?
RUNLEVEL - if runlevel of current page is smaller, or equal to RUNLEVEL, then you can freely read/write to this page.
Interrupts
Interrupts are uh, well, interrupts. They interrupt CPU execution, just like routine calls.
Main use of interrupts - handling errors. In extended mode instead of stopping execution,
CPU will "call" one of interrupt handlers specified in interrupt table pointed by IDTR.
You can handle CPU errors, or use interrupts as another way to call certain functions. You can have up to 256 interrupts.
There is special type of interrupts - NMI interrupt, which is kind of hardware interrupt that can be called
externally at any time. Main difference - it stores entire state of CPU prior call, and restores after return.
Non-maskable interrupts
NMI's are called by triggering value on NMI input of CPU (value in range of 32..255).
When NMI call arrives processor stores entire state (all registers and segment registers)
and calls NMI routine. NMI can be anything in interrupt table (interrupts 32..255).
NMI calls are same as interrupt calls, except you should exit them with "NMIRET".
If the interrupt call was NMI call, then interrupt parameter is set to 1, else it's set to 0.
Interrupt table
Interrupt table holds entry points and parameters to all interrupts. In total there is max of 256 interrupts numbered 0..256.
If interrupt is not defined in interrupt table, then it's ignored, except:
Interrupt #0 resets the CPU (when not handled)
Interrupt #1 pauses the CPU (CLK = 0) (when not handled)
Table format:
Code:
IDTR points here
V
IP | CS | 0 | FLAGS ||IP | CS | 0 | FLAGS ||...........|
|-----------------------------||------------------------------||..|..|..|..|
Interrupt #1 Interrupt #2
Flags
Code:
BIT|VALUE| Description
---|-----|------------------------------------------------------------------
3 | 8 | CMPR is set to 1 if interrupt was handled, and to -1 if it wasn't
4 | 16 | Interrupt does not set CS
5 | 32 | Interrupt enabled
Interrupt calls
Interrupt calls store return address and return segment on stack. You should always return from interrupts
by using IRET opcode (although RETF has same behaviour).
Interrupts have error parameter, which is passed into LADD register. You can read it with CPUGET instruction.
Interrupts are active only in EXTENDED MODE (EF = 1), else CPU will stop on each error/interrupt.
Debug trap interrupt never shuts down execution though, and can be used for debugging purposes (breakpoint).
Execution sequence
1. Fetch opcode and RM
2. Decode RM byte for param 1 and 2
3. Execute opcode
4. Write back into first parameter
Interrupts may occur on any of these stages. If they do, rest of stages are ignored.
RM value and parameter modes:
Each opcode can have 0, 1 or 2 parameters. Parameters are determined by RM value. RM value consists of 2 two-digit values,
corresponding to parameter 1 and parameter 2. RM may point to immediate value, memory via displacement, register, memory via register.
RM values:
Code:
RM | Description | Example
---------|-------------------------------------------------------|-------------
0 | Direct value (follows RM) | MOV 123
1..8 | General registers #1..#8 | MOV EAX
17..24 | Memory access via general registers #1..#8 | MOV #EAX
25 | Memory access via displacement (direct value) | MOV #123
26..33 | General register #1..#8 + segment register | MOV ES:EAX
34..41 | Memory access via displacement+general register #1..#8| MOV 123:#EAX
42..49 | General register #1..#8 + direct value | MOV 123:EAX
1000-2024| Ports 0-1023 on IO Bus | MOV PORT123
RealRM = RM[param1] + RM[param2]*10000
Ports
Ports must be attached to IOBus output. Any hi-speed compatible device will work. Use data port for default 8 ports (i/o).
Port read is equal to read on memory bus. Port write is equal to write on memory bus.
Default error codes/error interrupts
Code:
Value | Meaning
------|------------------------------------------------------------------------
2 | End of program execution
3 | Division by zero
4 | Unknown opcode
5 | Internal processor error
6 | Stack error (overflow/underflow)
7 | Memory read/write fault
8 | MemBus fault
9 | Write access violation (page protection)
10 | Port read/write fault
11 | Page acccess violation (page protection)
12 | Read access violation (page protection)
13 | General processor fault
14 | Execute access violation (page protection)
15 | Address space violation
31 | Debug trap
Chapter 2: Instruction set reference
Instruction set, for ZCPU 4.00:
Code:
BYTE| MNEMONIC | DESCRIPTION
----|------------|-------------------------------------------------------------
1 | JNE X | IP = X, IF CMPR ~= 0
1 | JNZ X | IP = X, IF CMPR ~= 0
2 | JMP X | IP = X
3 | JG X | IP = X, IF CMPR > 0
3 | JNLE X | IP = X, IF !(CMPR <= 0)
4 | JGE X | IP = X, IF CMPR >= 0
4 | JNL X | IP = X, IF !(CMPR < 0)
5 | JL X | IP = X, IF CMPR < 0
5 | JNGE X | IP = X, IF !(CMPR >= 0)
6 | JLE X | IP = X, IF CMPR <= 0
6 | JNG X | IP = X, IF !(CMPR > 0)
7 | JE X | IP = X, IF CMPR = 0
7 | JZ X | IP = X, IF CMPR = 0
8 | CPUID X | EAX -> CPUID[X]
9 | PUSH X | WRITE(ESP+SS,X); ESP = ESP + 1
----|------------|-------------------------------------------------------------
10 | ADD X,Y | X = X + Y
11 | SUB X,Y | X = X - Y
12 | MUL X,Y | X = X * Y
13 | DIV X,Y | X = X / Y
14 | MOV X,Y | X = y
15 | CMP X,Y | CMPR = X - Y
16 | <RESERVED> |
17 | <RESERVED> |
18 | MIN X,Y | MIN(X,Y)
19 | MAX X,Y | MAX(X,Y)
----|------------|-------------------------------------------------------------
20 | INC X | X = X + 1
21 | DEC X | X = X - 1
22 | NEG X | X = -X
23 | RAND X | X = Random(0..1)
24 | LOOP X | IF ECX ~= 0 THEN JUMP X
25 | LOOPA X | IF EAX ~= 0 THEN JUMP X
26 | LOOPB X | IF EBX ~= 0 THEN JUMP X
27 | LOOPC X | IF EDX ~= 0 THEN JUMP X
28 | SPG X | PAGE(X) = READ ONLY
29 | CPG X | PAGE(X) = READ AND WRITE
----|------------|-------------------------------------------------------------
30 | POP X | X <- STACK
31 | CALL X | IP -> STACK; IP = X
32 | BNOT X | X = BINARY NOT X
33 | FINT X | X = FLOOR(X)
34 | FRND X | X = ROUND(X)
35 | FFRAC X | X = X - FLOOR(X)
36 | FINV X | X = 1 / X
37 | HALT X | HALT UNTIL PORT[X]
38 | FSHL X | X = X * 2
39 | FSHR X | X = X / 2
----|------------|-------------------------------------------------------------
40 | RET | IP <- STACK
41 | IRET | IP <- STACK
42 | STI | IF = TRUE
43 | CLI | IF = FALSE
44 | STP | PF = TRUE
45 | CLP | PF = FALSE
46 | <RESERVED> |
47 | RETF | IP,CS <- STACK
48 | STE | EF = TRUE
49 | CLE | EF = FALSE
----|------------|-------------------------------------------------------------
50 | FAND X,Y | X = X AND Y
51 | FOR X,Y | X = X OR Y
52 | FXOR X,Y | X = X XOR Y
53 | FSIN X,Y | X = SIN Y
54 | FCOS X,Y | X = COS Y
55 | FTAN X,Y | X = TAN Y
56 | FASIN X,Y | X = ASIN Y
57 | FACOS X,Y | X = ACOS Y
58 | FATAN X,Y | X = ATAN Y
59 | MOD X,Y | X = X MOD Y
----|------------|-------------------------------------------------------------
60 | BIT X,Y | CMPR = BIT(X,Y)
61 | SBIT X,Y | BIT(X,Y) = 1
62 | CBIT X,Y | BIT(X,Y) = 0
63 | TBIT X,Y | BIT(X,Y) = ~BIT(X,Y)
64 | BAND X,Y | X = X BAND Y
65 | BOR X,Y | X = X BOR Y
66 | BXOR X,Y | X = X BXOR Y
67 | BSHL X,Y | X = X BSHL Y
68 | BSHR X,Y | X = X BSHR Y
69 | JMPF X,Y | CS = Y; IP = X
----|------------|-------------------------------------------------------------
70 | NMIINT X | NMIINTERRUPT(X);
71 | CNE X | CALL(X), IF CMPR ~= 0
71 | CNZ X | CALL(X), IF CMPR ~= 0
72 | <RESERVED> |
73 | CG X | CALL(X), IF CMPR > 0
73 | CNLE X | CALL(X), IF !(CMPR <= 0)
74 | CGE X | CALL(X), IF CMPR >= 0
74 | CNL X | CALL(X), IF !(CMPR < 0)
75 | CL X | CALL(X), IF CMPR < 0
75 | CNGE X | CALL(X), IF !(CMPR >= 0)
76 | CLE X | CALL(X), IF CMPR <= 0
76 | CNG X | CALL(X), IF !(CMPR > 0)
77 | CE X | CALL(X), IF CMPR = 0
77 | CZ X | CALL(X), IF CMPR = 0
78 | MCOPY X | X BYTES(ESI) -> EDI
79 | MXCHG X | X BYTES(ESI) <> EDI
----|------------|-------------------------------------------------------------
80 | FPWR X,Y | X = X ^ Y
81 | XCHG X,Y | X,Y = Y,X
82 | FLOG X,Y | X = LOG(Y)
83 | FLOG10 X,Y | X = LOG10(Y)
84 | IN X,Y | X = PORT[Y]
85 | OUT X,Y | PORT[X] = Y
86 | FABS X,Y | X = ABS(Y)
87 | FSGN X,Y | X = SIGN(Y)
88 | FEXP X,Y | X = EXP(Y)
89 | CALLF X,Y | CS = Y; CALL(X)
----|------------|-------------------------------------------------------------
90 | FPI X | X = PI
91 | FE X | X = E
92 | INT X | INTERRUPT(X)
93 | TPG X | CMPR = TEST PAGE(X)
94 | FCEIL X | X = CEIL(X)
95 | ERPG X | ERASE ROM PAGE(X)
96 | WRPG X | WRITE ROM PAGE(X)
97 | RDPG X | READ ROM PAGE(X)
98 | TIMER X | X = TIMER
99 | LIDTR X | IDTR = X
100 | <RESERVED> |
----|------------|-------------------------------------------------------------
101 | JNER X | IP = IP+X, IF CMPR ~= 0
101 | JNZR X | IP = IP+X, IF CMPR ~= 0
102 | JMPR X | IP = IP+X
103 | JGR X | IP = IP+X, IF CMPR > 0
103 | JNLER X | IP = IP+X, IF !(CMPR <= 0)
104 | JGER X | IP = IP+X, IF CMPR >= 0
104 | JNLR X | IP = IP+X, IF !(CMPR < 0)
105 | JLR X | IP = IP+X, IF CMPR < 0
105 | JNGER X | IP = IP+X, IF !(CMPR >= 0)
106 | JLER X | IP = IP+X, IF CMPR <= 0
106 | JNGR X | IP = IP+X, IF !(CMPR > 0)
107 | JER X | IP = IP+X, IF CMPR = 0
107 | JZR X | IP = IP+X, IF CMPR = 0
108 | LNEG X | X = LOGIC NEGATE(X)
109 | <RESERVED> |
----|------------|-------------------------------------------------------------
110 | NMIRET | NMIRESTORE;
111 | IDLE | FORCE_CPU_IDLE;
112 | NOP | <does nothing>
113 | <RESERVED> |
114 | <RESERVED> |
115 | <RESERVED> |
116 | <RESERVED> | <please dont even attempt using this>
117 | <RESERVED> |
118 | <RESERVED> |
119 | <RESERVED> |
----|------------|-------------------------------------------------------------
120 | CPUGET X,Y | X = CPU[Y]
121 | CPUSET X,Y | CPU[X] = Y
122 | SPP X,Y | PAGE[X].Y = 1
123 | CPP X,Y | PAGE[X].Y = 0
124 | SRL X,Y | PAGE[X].RunLevel = Y
125 | GRL X,Y | X = PAGE[Y].RunLevel
126 | LEA X,Y | X = ADDRESS(Y)
CPUID
Code:
X | EAX meaning | Default value
------|--------------------------------|-----------------------|
0.0 | CPU ID/Version | 688
1.0 | On-board RAM size | 65536
2.0 | Type (0 - ZCPU; 1 - ZGPU) | 0
CPUID is used for determining CPU version and type. This is really useful for checking code compatibility.
Old code is guaranteed to run on new versions of CPU, unless it depends on critical errors and flaws in CPU design.
ZyeliosASM2 documentation
ZyeliosASM2 uses assembler language, and its syntax is pretty close to such of popular assemblers, like NASM.
There are opcodes (commands for processor), opcode parameters and labels/variables/defines/macros.
If there are more than 2 opcodes/variables/defines/macros on line they can be seperated with ; symbol (optional)
OPCODES SYNTAX
Code:
<opcode> <parameter1>, <parameter2>
Opcode is one of processors opcodes (info about opcodes is available in ZyeliosCPU documentation).
Parameter1 and Parameter2 are parameters. Certain opcodes have 0, 1, or all 2 parameters.
Example:
PARAMETERS SYNTAX
ZyeliosASM can take various things as opcode parameters.
Here are possible values:
* EAX,EBX,ECX,EDX,ESI,EDI,ESP,EBP - Value of one of general registers with same name.
* PORT0,PORT1,...,PORT1023 - Value of one of ports.
Notice: when CPU reads from port, it uses input port.
When CPU performs write, it writes directly to output port.
You must connect device that supports ports you want to use,
for example data port can be used to access 8 lower ports.
Port space acts exactly like address space
This is why MOV PORT0,PORT1; will set value of port 1 in out
port 0. Single-opcode operands, for example NEG, will read
value from INPUT and then write into same port in OUTPUT.
There must be no spaces between comma and parameters.
* <NAME> - Using define name, label name, or variable name
will be replaced with labels/variables address,
or define value.
* #<NAME> - This will read value in internal memory from
address specified by name. Name might be
variable name, or general purpose register.
SEGMENT PREFIX SYNTAX
LABELS SYNTAX
Regular labels are defined as:
Local labels (they are accessible only in nearest code around):
Global lables are defined as:
Global labels are not wiped with "wipe_labels", or between ASM files (result after some high-level ZASM linkers)
Example:
Code:
mainloop:
@local:
jmp @local;
jmp local; //both work
jmp mainloop;
VARIABLES & VARIABLE SYNTAX
Variables are values in memory. Variables can be single value or array of values.
Variables are defined using ALLOC macro.
Variable value can be read at any time using "#<variablename>" syntax.
Example:
Code:
mov eax,#somevar;
alloc somevar;
"ALLOC" MACRO
Alloc macro will create new variable, and set it to zero.
Alloc writes this variable in code, thats why you cant define
variables inside executing code, yet.
Alloc can be used in 4 ways:
alloc; - will allocate 1 value and set it to zero
alloc <value>; - will allocate <value> values, and zero them out
alloc <name>; - will allocate 1 value with specific name
alloc <name>,<value>; - will allocate array with specific name and <value> values
alloc <name>,<value>,<value2>; - will allocate array with name and set its members to <value2>
DEFINE MACRO
This macro will create new value definition, which can be used as parameter in future.
Syntax:
Code:
define <name>,<value>;
This will create new definition with <name> and <value>
Example:
Code:
define smth,4;
mov eax,smth; //This will compile into mov eax,4;
"ORG" and "OFFSET" MACROS
ORG macro will change code write position to specific one. If ORG is first operand, it can be used to specify code offset.
OFFSET macro will offset all addresses that you use in your code by specific constant
Syntax:
Code:
ORG <offset>;
OFFSET <delta_offset>;
Example:
jmp 123; //true meaning: jmp 123
offset 100;
jmp 123; //true meaning: jmp 223
"DB" MACRO
DB macro is used to put fixed arrays of values or strings into your
code. Syntax 1 shows how to make arrays of bytes, syntax 2 shows
string*, and syntax 3 shows mixed. You can use labels in DB statements;
* - You may want your strings to be null-terminated (end with 0) to mark
end of string
Syntax 1:
Code:
DB <value1>,<value2>,...;
Syntax 2:
Syntax 3:
Code:
DB '<string1>',<value1>,'<string2>',<value2>,...;
"DATA" & "CODE" MACROS
Data macro is equal to this code:
Code:
DATASTART:
JMP CODESTART;
CODE macro is equal to this code:
You must either use both macros, or do not use them at all, because
data macro makes code to start working from code macro if placed in start
of program
COMMENTS SYNTAX
Right now only one way of commenting is available:
Putting "//" (double right slash) will make compiler ignore rest of line after "//".
GPU MACROS
General syntax for extra GPU-specific macros is:
Code:
<basictype> <name>,<x>,<y>,....; //initialize default value
<basictype> <name>; //initialize to [0;0...]
basictype is one of basic types:
- float, scalar, vector1 - 1 byte (float <name>,<f>
- vector2f, vector, uv - 2 bytes (vector <name>,<x>,<y>; uv <name>,<u>,<v>
- vector3f - 3 bytes (vector3f <name>,<x>,<y>,<z>
- vector4f - 4 bytes (vector4f <name>,<x>,<y>,<z>,<w>
- color - 4 bytes, alpha optional to specify (color <name>,<r>,<g>,<b>,<a>; color <name>,<r>,<g>,<b>
SERVICE MACROS
- wipe_locals - clears all local variables in current scope
- wipe_labels - clears all non-global variables in current scope
- setvar - set compiler variable ("localrange" for local variable scope range, "returnregister" to set return register, see below)
- asmfile/asmend - internally used by certain linkers for error reporting
Syntax:
Code:
wipe_locals;
wipe_labels;
setvar localrange,640; //set local range to +-640 bytes
setvar returnregister,ebx; //return values in ebx, see below
[size=4]HIGH LEVEL FUNCTION DEFINITION AND C-STYLE CALLING[/b]
This is an experimental, and very limited way of auto-generating C-style functions. They are compatible with ZC32.
Function returns value in EAX register, and there is "return" macro for that. It also generates "ret" instruction. For details of precise code generated by ZASM, scroll below.
Syntax:
Code:
function <functionname>(<param1>,<param2>,...)
function <functionname>()
function <functionname>
Calling function is kind of like in other high-level language, except that parameters should be valid parameters for opcode.
Let the examples demonstrate:
Code:
function add(a,b)
mov eax,a;
add eax,b;
return eax;
end
add(ebx,ecx); //EAX = EBX + ECX now
add(1+1,ecx); //sorry, INVALID
add(#eax,#var); //valid
add(ss:eax,es:#var); //valid
PLEASE: PUSH AND POP REGISTERS YOU USE. RESTRAIN FROM USING EAX, ECX, AND EBP REGISTERS...
Actual code generated by "function" macro:
Function definition:
Code:
function add(a,b)
<code>
end
turns into
Code:
add:
push ebp
mov ebp,1:esp
<code>
pop ebp
ret
Function calling:
turns into
Code:
mov ecx,2;
call add;
add esp,2;
No living person on earth has got the function macros to work, so wait till I say they fully work
Wiring the CPU
Inputs:
- Clk - CPU Power/Execution
- Reset - Reset execution, set Clk to 0 (must be re-triggered)
- Frequency - CPU frequency in relative hertz (Hz)
- MemBus - Link to any output of hi-speed device to link it to top of address space
- IOBus - Link to any output of hi-speed device to link it to port space of CPU
- NMI - Non-maskable interrupt, see "Interrupts" chapter
Outputs:
- Error/Memory - Error code/Hi-Speed link output
Further reading
//todo:
ZCPU Documentation 
I am trying to learn the language but it's just so different from C++ or Visual basic which I have 'some' experience with the syntax. I'm not sure i get the syntax though even though i have read all the documentation several times!
However I am starting to come to terms with the context it is still confusing but I can get it to add two values together so it's a start
re;overflow:auto'>loop:
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